1. Field of the Invention
This invention relates to a semiconductor device and a method of producing the same, and more specifically to a semiconductor device comprising a semiconductor film having a planar surface and a method of producing such a semiconductor device.
2. Description of Related Art
A method of producing a thin film transistor (hereinafter referred to as a “TFT”) will be described.
FIG. 1 depicts the condition of the surface of a polycrystallized silicon film. FIGS. 2A to 2D respectively depict cross sectional views taken along line A—A of FIG. 1 for showing production processes of a conventional TFT.
Step 1 (FIG. 2A):
On an insulating substrate 10 composed of a glass, a silica glass, or the like, an insulating film 11 composed of a single SiO2 film or of an SiN film and an SiO2 film is formed, and an amorphous silicon film (hereinafter referred to as an “a-si film”) 12 is further formed thereon using a CVD method.
Step 2 (FIG. 2B):
The a-Si film 12 is annealed by irradiating the a-Si film 12 with linear excimer laser 14 such as XeCl, KrF, and ArF by scanning from one direction to another, so that the a-Si film 12 is fused and recrystallized for polycrystallization, to thereby form a polysilicon film (hereinafter referred to as a “p-Si film”) 13.
At this time, irradiation of a surface of the a-Si film 12 with an excimer laser beam 14 in the direction shown by an arrow while scanning the a-Si film 12 causes the a-Si film 12 to be fused for recrystallization. Namely, the a-Si film 12, which is heated and fused by the laser radiation 14, is then cooled and recrystallized, thereby forming a p-Si film 13. At this time, however, grain boundaries in the crystal collide with each other causing these areas protrude as shown by projections 100.
Step 3 (FIG. 2C):
A gate insulating film 14 composed of an SiO2 film is then formed over the entire surface of the p-Si film 13 using the CVD method. A metal film made of a refractory metal such as chromium (Cr) and molybdenum (Mo) is further formed thereon by a spattering method, and is processed into a predetermined shape by means of photolithography and a dry etching technology using RIE (Reactive Ion Etching), to thereby form gate electrodes 15.
Subsequently, for forming a P channel TFT, P type ions such as boron (B) are implanted (doped) with regard to the p-Si film 13 via the gate insulating film 14, with the gate electrodes 15 used as a mask. When an N type TFT is to be formed, on the other hand, N type ions such as phosphorous (P) are implanted in a similar manner. Thus, a portion of the p-Si film 13, which is an active layer, covered by the gate electrode 15 functions as a channel region 13c, and portions on both sides of the channel region 13c are a source region 13s and a drain region 13d, respectively.
An interlayer insulating film 16 formed from a single SiO2 film or from two layers including SiO2 and SiN films is further disposed using the CVD method.
Step 4 (FIG. 2D):
First contact holes 17 are then formed at locations corresponding to the drain region 13d and the source region 13s, respectively, such that they run through the interlayer insulating film 16 and the gate insulating film 14 to reach the p-Si film 13. Then, drain and source electrodes 19d, 19s, each composed of a multi-metal layer including aluminum and titanium in this order, are formed at the respective first contact holes 17 by patterning the deposited aluminum and titanium, by spattering, on the interlayer insulating film 16 through which each of the first contact holes 17 is formed, and which fills the first contact hole 17, for example.
Over the interlayer insulating film 16 on which the drain electrode 19d and the source electrode 19s are thus formed and over the drain and source electrodes 19d and 19s, a planarizing insulating film 20 is further disposed for surface planarization. The planarizing insulating film 20 is formed of an acrylic resin layer, which in turn is formed by applying and baking an acrylic resin solution. This acrylic resin layer can smooth the unevenness caused by the gate electrode 15 and the drain and source electrodes 19d and 19s, and planarize the surface.
Over the source electrode 19s, a second contact hole 21 is formed which passes through the acrylic resin layer, which is a planarizing insulating film 20. A pixel electrode 22 is then formed at the portion of this second contact hole 21 such that this electrode connects to the source electrode 19ss and extends over the acrylic resin layer. The pixel electrode 22 is formed in the following manner. A transparent conductive film, which is an ITO (Indium Tin Oxide) for example, is first disposed on the planarizing insulating film 20 having the second contact hole 21 formed therethrough. After a resist film is applied over the transparent conductive film in a predetermined electrode pattern, the exposed portion of the transparent conductive film is etched by a dry etching method such as the RIE method using HBr gas and Cl2 as etching gas, to thereby form the pixel electrode 22.
TFTs produced in the above-described manner suffer from problems. As already described, when the a-Si film is fused and recrystallized by laser beam irradiation, the grain boundaries of the crystal collide with each other causing the surface of the p-Si film 13 to have projections 100. Therefore, the gate insulating film 14 formed above these projections has a smaller thickness at these projections 100. These projections can be as thick as the p-Si film. When the thickness of the p-Si film 13 is approximately 400 Å, for example, the projection may be as thick as 400 Å. This leads to a disadvantage that sufficient insulation may not be achieved between the p-Si film 13 and the gate electrode 15, or that, when the height of projection 100 is larger than the thickness of the gate insulating film 14, there is a short circuit between the p-Si film 13 and the gate electrode 15.
Further, concentration of electric field in the projection 100 due to applied voltages causes dielectric breakdown, which also results in possibility of short circuit between the p-Si film 13 and the gate electrode 15.
In addition, even when a uniform gate voltage is applied to the gate electrodes 15, a voltage which is actually applied to the p-Si film 13 varies within a surface of the insulating substrate. This results in a TFT having non-uniform characteristics. When such a TFT is employed in a display device such as a liquid crystal display, there is a possibility that variations in display characteristics are caused within the display screen.